The present invention relates to a floating-point adder, a semiconductor device, and a control method for a floating-point adder. For example, the present invention relates to a floating-point adder, a semiconductor device, and a control method for a floating-point adder for adding floating-point numbers.
An image recognition program extracts feature vectors from an image and makes a determination and calculation of the feature vectors using dictionary vectors for determination. The main operation in the determination calculation is a calculation of a high-dimensional vector dot product. A vector dot product is calculated by continuously performing a huge number of product-sum arithmetic operations. To efficiently execute the processing of continuously performing product-sum arithmetic operations, an addition is performed by an accumulator including a register that holds previous accumulation results. It is necessary to perform the addition in one cycle so that the accumulation is performed every cycle. The floating-point representation has a large dynamic range, and thus the floating-point representation has been mainly used as a way of representing vector elements. A floating point is a number representation composed of a 1-bit sign, an exponent and a mantissa of a fixed length.
Japanese Unexamined Patent Application Publication No. H11-102353 discloses a technique relating to a floating point product sum arithmetic logic unit. The floating point product sum arithmetic logic unit disclosed in Japanese Unexamined Patent Application Publication No. H11-102353 includes a floating-point multiplier, a digit alignment shifter, a mantissa adder, and an intermediate result register. The digit alignment shifter aligns the digits of the intermediate result of the previous product-sum arithmetic operation, which is stored in the intermediate result register, and the digits of the multiplication result of the floating-point multiplier. The mantissa adder adds the two mantissas, the digits of which are aligned by the digit alignment shifter, and stores the addition result in the intermediate result register as the intermediate result of the product-sum arithmetic operation.